1. Field
This disclosure relates generally to scan testing, and more specifically, to scan testing with staggered clock.
2. Related Art
Scan testing of a system on a chip (SoC) is commonly used to perform at-speed transition pattern based testing. Electronic design automation (EDA) tools use Automatic Test Pattern Generation (ATPG) to generate and provide scan patterns to scan chains of on SoC. For scan testing, scan patterns are shifted into scan chains during a shift phase in which a shift clock is used to control the shifting of the scan chains, and a capture clock is used for at-speed transition testing during capture phases. Within an SoC, each core may have any number of scan chains. The capture clock in each core is controlled by a corresponding capture clock control chain. Scan testing for SoCs has been improved by the reuse of generated scan patterns at the core level. For example, multiple cores on an SoC may reuse the same scan patterns. However, for at-speed transition pattern based testing, there can be a current-resistance (IR) drop issue during the capture phases of the scan testing when multiple cores are scan tested in parallel and the capture clocks are aligned.
One solution to the IR issues for parallel scan testing of multiple cores is to use different test pattern data controlling the capture clocks to reduce their alignment. However, the need for different test pattern data for controlling the capture clocks prevents the ability to retarget the received test patterns at one set of input pins of the SoC by simply fanning out the test patterns to all cores. That is, each core requires different test pattern data to be loaded into each core's capture clock control chain. This increases cost and complexity of the SoC and of scan pattern generation. Therefore, a need exists for improved scan testing which reduces IR drop due to the capture clocks.